Qualcomm is a global leader in wireless technology, known for pioneering 5G, AI, and IoT solutions that power billions of devices worldwide. With a strong R&D focus and a culture of innovation, Qualcomm offers a dynamic environment where engineers get to work on cutting‑edge semiconductor products that shape the future of connectivity. The company’s Indian operations, spread across Bengaluru, Hyderabad, and other tech hubs, serve as critical nodes for design, verification, and support of Qualcomm’s silicon portfolio. Joining Qualcomm means becoming part of a diverse, high‑performance team that values continuous learning, collaboration, and impact. The STA Engineer, Associate role is an entry‑level position that sits at the heart of the chip design flow. Static Timing Analysis (STA) is essential for ensuring that digital designs meet timing constraints before silicon fabrication. As an STA Engineer, you will assist senior engineers in analyzing timing paths, generating reports, and collaborating with design teams to achieve timing closure. This role offers a solid foundation in VLSI/ASIC design and opens pathways to advanced positions such as Timing Closure Engineer, Design Verification Engineer, or ASIC Design Engineer. **Key Responsibilities** 1. Support day‑to‑day Static Timing Analysis activities for ASIC/SoC projects. 2. Analyze critical timing paths, identify violations, and suggest corrective actions. 3. Generate timing reports and assist in debugging timing‑related issues. 4. Work closely with RTL, synthesis, and physical design teams to achieve timing closure. 5. Validate design constraints and ensure they align with product specifications. 6. Participate in sign‑off activities and documentation of timing results. 7. Contribute to the development and maintenance of STA scripts and automation tools. 8. Assist in post‑silicon validation by correlating silicon timing with pre‑silicon analysis. 9. Keep abreast of the latest STA methodologies, tools, and semiconductor technologies. 10. Collaborate in cross‑functional meetings to communicate timing status and risks. **Tech Stack & Tools**: Synopsys PrimeTime, Cadence Tempus, TCL/Python scripting, Linux environment, basic knowledge of digital design languages (Verilog/VHDL), and familiarity with design constraint formats (SDC). **Growth Path**: Starting as an Associate, you can progress to Senior STA Engineer, Timing Closure Lead, or move laterally into ASIC Design, Verification, or Physical Design roles, depending on interest and performance. Qualcomm’s internal training programs, mentorship, and exposure to global projects accelerate career growth. **Why Join Qualcomm?** The company offers exposure to world‑class technology, a collaborative culture, and opportunities to work on products that impact billions of users. Fresh graduates gain hands‑on experience with industry‑standard tools, mentorship from seasoned engineers, and a clear roadmap for professional advancement.