Physical Design Layout Engineer

Intel Corporation, a global leader in semiconductor manufacturing and computing innovation, has a strong foothold in India with multiple R&D centers, design studios, and manufacturing collaborations. The Bangalore campus focuses on cutting‑edge chip design, advanced process development, and next‑generation architecture that powers everything from data centers to consumer devices. Intel’s Indian engineering teams work closely with global product groups, offering fresh graduates exposure to world‑class technology, cross‑functional collaboration, and a culture that encourages continuous learning. The role of Physical Design Layout Engineer is a core part of Intel’s semiconductor engineering business. As a fresher, you will join a team that translates logical netlists into physical silicon layouts, ensuring that the design meets performance, power, and reliability targets. You will be mentored by senior layout engineers and will get hands‑on experience with industry‑leading EDA tools, design rule checks, and verification flows. The position is hybrid, allowing you to work from the Bangalore office while also leveraging remote resources for focused design tasks. Key responsibilities include: 1. Develop semi‑custom cell and block level layouts using ICC2 and related tools. 2. Perform floor‑planning at the functional unit block (FUB) level and generate abstract views for higher‑level integration. 3. Execute schematic‑to‑layout verification (DRC, LVS) to ensure design integrity. 4. Conduct parasitic extraction and analyze its impact on timing and power. 5. Create and edit custom polygons, and fine‑tune routing using auto‑place & route algorithms. 6. Collaborate with circuit designers, verification engineers, and process engineers to resolve layout‑related issues. 7. Contribute to the development and improvement of physical design methodologies and verification flows. 8. Participate in full‑chip assembly activities, including placement, routing, and sign‑off. 9. Write and maintain TCL scripts to automate repetitive tasks and improve productivity. 10. Document design decisions, maintain layout libraries, and ensure compliance with Intel’s design standards. Tech stack: Synopsys ICC2, TCL scripting, Cadence Virtuoso (for custom editing), Mentor Graphics Calibre for DRC/LVS, and internal Intel design automation frameworks. The role offers a clear growth path – starting as a Junior Layout Engineer, progressing to Senior Layout Engineer, then to Physical Design Lead or Architecture Specialist, with opportunities to move into cross‑functional system design or project management roles. Why join Intel? Intel provides a vibrant ecosystem of learning – from internal training modules to mentorship programs – that accelerates a fresher’s technical depth. The company’s commitment to diversity, work‑life balance, and employee well‑being makes it an attractive place to start a career. Moreover, working on real silicon projects gives you a tangible impact on products that shape the future of computing.